AMD-761 Datasheet, PDF (215/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
5.2.2
5.2.3
PCI Chaining
PCI chaining is a feature designed to optimize memory writes
from the processor to the PCI bus. Chaining simply causes
write combining at the PCI interface, such that four quadword
CPU memory writes to contiguous addresses are chained
together, resulting in a single PCI burst-write instead of
separate nonburst writes.
PCI chaining is enabled by the PCI_Chain_En bit in the PCI
Arbitration Control register (Dev 0:F0:0x84). It is
recommended that this bit always be set for optimal
performance.
PCI Bus Parking
The PCI Local Bus Specification, Revision 2.2, requires that a
default bus owner be designated that always drives the bus to a
known value to prevent the bus from floating for long idle
periods. The AMD-761 system controller provides two options
for bus parking:
„ Park on the AMD-761 system controller—that is, CPU
accesses to PCI agents
„ Park on the last master that had bus tenure
Arbitration latency on an idle bus for the agent that has
default ownership (bus is parked on that agent) is zero PCI
clocks, whereas it is two PCI clocks for all other masters.
PCI bus parking is controlled by the Park_PCI bit in the PCI
Arbitration Control register (Dev 0:F0:0x84). It is
recommended that this bit be cleared to 0 to force parking the
bus on the AMD-761 system controller.
Chapter 5
PCI Bus Interface
203