AMD-761 Datasheet, PDF (27/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
2.2.2
2.2.3
IACK
In x86 compatible Socket2000 systems, APIC is used as the
interrupt controller. To fetch the appropriate vector during
IACK cycles, x86 processors are required to assert their APIC
ID (CPU ID) on bits [15:12] of the address field when reading
the IACK generation space. IACK return data flushes all PCI
and AGP/PCI write buffers to memory.
PCI Configuration Accesses
In legacy x86 PC systems, PCI configuration cycles are
generated via an indirect method. A configuration address
register is defined at I/O address 0CF8 that allows software to
load a value that is asserted on the PCI address wires during
the next configuration read/write cycle. A configuration data
register is defined at I/O address 0CFC that allows software to
generate configuration read and write cycles on the PCI using
IN and OUT instructions. Data sent during OUT instructions to
the Configuration Data register is asserted on the PCI data
wires during the generated configuration write transaction.
Data received in response to a generated configuration read
transaction is returned to satisfy the IN from the Configuration
Data register.
In Socket2000 systems, PCI configuration cycles are generated
in one of two ways:
„ In EV6 Compatible mode, the x86 processor must detect IN
and OUT instructions that reference 0CF8 and 0CFC and
generate the appropriate, explicit RdBytes/Rd/LWs and
WrBytes/WrLWs Socket2000 commands to a 16-Mbyte
region as follows:
• When an OUT instruction is detected to 0CF8, the write
data is saved into a register and the instruction retired.
• When an IN/OUT instruction is detected to 0CFC, an
appropriate AMD Athlon system bus Rd/Wr transaction is
launched with the SysAdd Field[23:0] taken from the
register that saved the most recent write to 0CF8 (above).
„ In traditional mode, which the AMD-761 system controller
implements, IN and OUT instructions that reference 0CF8
and 0CFC are passed normally on to the AMD Athlon
processor system bus where the Northbridge generates the
appropriate PCI configuration access.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
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