AMD-761 Datasheet, PDF (150/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
2.5
2.5.1
Memory-Mapped Registers
The AMD-761 system controller implements a set of memory-
mapped control registers as shown in Section 2.5.2 on page 140.
The base for these registers is defined in BAR1 (see
“Dev0:F0:0x14” on page 39). This address is determined and
loaded by system BIOS. The registers in the space are used by
the AMD-761 miniport driver to control the GART cache
functionality during run time.
AMD-761™ System Controller GART Cache Overview
This section provides a brief overview for programmers. The
Graphics Address Relocation Table (GART) is a structure in
memory that contains mappings from a virtual address
generated by an AGP master (or any other master in the system
including PCI masters and the CPU) and the actual physical
address of a given request. The default mode used by the
AMD-761 GART cache is a two-level directory/table indexing
scheme that is very similar to the standard x86 virtual memory
architecture. By using two levels of indexing, the GART
structure does not need to be physically contiguous. Figure 4
on page 139 illustrates the two-level indexing scheme.
138
AMD-761™ System Controller Programmer’s Interface
Chapter 2