AMD-761 Datasheet, PDF (133/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31 PERR_Rcv
30 SERR_Rcv
29 Mas_ABRT
28 Trgt_ABRT
27
26–25
Trgt_ABRTS
_Signaled
DEVSEL_Timing
24 Data_PERR
23 Fast_B2B
22 UDF
21 66M
20 Cap_Lst
19–10 Reserved
9 FBACK
AGP/PCI Command and Status (Dev1:0x04)
Function
Detected Parity Error
This bit is always Low because the AMD-761™ system controller does not support
parity checking.
Signaled System Error
This bit is set whenever the AMD-761 system controller received AGP SERR# and
subsequently asserted PCI SERR#. This bit is cleared by writing a 1. Refer to Table 7 on
page 34 for details about SERR# assertion and status.
Received Master Abort
This bit is always 0.
Receive Target Abort
This bit is always 0.
Signaled Target Abort
This bit is always 0.
DEVSEL# Timing
This field is always 0b01, indicating that the AMD-761 system controller supports medium
DEVSEL# timing.
Data PERR#
This bit is always 0 because the AMD-761 system controller does not report data
parity errors.
Fast Back-to-Back Capable
This bit is always 0, indicating that the AMD-761 system controller as a target is not
capable of accepting fast back-to-back transactions when the transactions are not to the
same agent.
User-Definable Features
This bit is always 0, indicating that UDF is not supported on the AMD-761 system
controller.
66-MHz Capable
This bit is always 1, indicating that the AMD-761 system controller supports 66 MHz on
device 1.
Capabilities List
This bit is always 0, indicating that the configuration space of this device does not support
a capabilities list.
Reserved
Fast Back-to-Back to Different Devices Enable
This bit is always 0, because the AMD-761 system controller does not allow generation of
fast back-to-back transactions to different agents.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
121