AMD-761 Datasheet, PDF (84/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions (Continued)
PCI Arbitration Control (Dev0:F0:0x84)
Bit Name
Function
12 RD_Data_Err_ Read Data Error Disable
Dis
Whenever a cycle from a processor to the PCI or AGP buses results in a master abort
(except special cycles), the AMD-761™ system controller returns a read data error
indicator to the processor. When set, this bit causes data value of all 1s to be returned.
When clear, an AMD Athlon™ processor system bus read data error response is returned.
The CPU response to read data error is determined by the settings of the Machine Check
Architecture registers in the processor.
11 AGP_Erly_Prb_ AGP Early Probe Disable
Dis
As soon as the AMD-761 system controller detects a PCI write cycle to memory from an
external AGP master, it sends a “probe only” request to the processor that is used to flush
data from the processor cache. After one or more data phases, a write request is sent to
the memory, which also results in a probe. When set, this bit disables the early probe from
an AGP master running a PCI write cycle to memory.
10 PCI_Erly_Prb_ PCI Early Probe Disable
Dis
This bit is similar AGP_Erly_Prb_Dis and can disable early probe requests for write cycles
from an external master on the standard PCI bus.
9 AGP_Arb_Pipe_ AGP Arbiter Pipe Disable
Dis
When set, this bit disables the AGP arbiter from pipelining grants onto the bus.
8 SB_Lock_Dis Southbridge Lock Disable
When the Southbridge makes a request for the PCI bus, the AMD-761 system controller
makes sure that all the previous posted requests from the processors and PCI are
completed by the memory before granting the bus to the Southbridge. When set, this bit
disables this flushing of previous requests.
7 PM_Reg_En
Power Management Register Enable
This bit, when set, enables reading from and writing to the power management register
(at BAR2).
6 15M_Hole
15M Memory Hole
When set, this bit creates a hole in memory from 15 Mbytes to 16 Mbytes. This register is
used by the PCI decode logic to know when to accept a cycle from an external PCI master.
When set, the PCI decode logic does not assert a match for addresses falling in this range.
5 14M_Hole
14M Memory Hole
When set, this bit creates a hole in memory from 14 Mbytes to 15 Mbytes. This register is
used by the PCI decode logic to know when to accept a cycle from an external PCI master.
When set, the PCI decode logic does not assert a match for addresses falling in this range.
4 EV6_Mode
EV6 Mode
When set, this bit indicates that the PCI interfaces have to decode memory hits in the EV6
mode. There are no memory holes and DMA can be done to any address that lies within
the SDRAM map.
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AMD-761™ System Controller Programmer’s Interface
Chapter 2