AMD-761 Datasheet, PDF (146/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
AGP/PCI I/O Limit and Base Upper 16 Bits
Dev1:0x30
31
30
29
28
27
26
25
24
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
23
22
21
20
19
18
17
16
Bit
I/O_Lim[23:16]
Reset
0
0
0
0
0
0
0
0
R/W
R/W
15
14
13
12
11
10
9
8
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
7
6
5
4
3
2
1
0
Bit
I/O_Base[23:16]
Reset
0
0
0
0
0
0
0
0
R/W
R/W
Register Description
This set of registers define the valid range of 32-bit I/O addresses that are allowed to be forwarded from the host to the
AGP/PCI. Note that if this register is 0, 32-bit addressing mode is effectively disabled.
Bit Definitions
Bit Name
31–24 Reserved
23–16 I/O_Lim[23:16]
15–8 Reserved
7–0 I/O_Base[23:16]
AGP/PCI I/O Limit and Base Upper 16 Bits (Dev1:0x30)
Function
Reserved
I/O Limit
This field defines the upper limit (inclusive) of 24-bit I/O addresses that are passed to the
AGP/PCI bus.
Reserved
I/O Base
This field defines the base (inclusive) of 24-bit I/O addresses that are passed to the
AGP/PCI bus.
Programming Notes
134
AMD-761™ System Controller Programmer’s Interface
Chapter 2