AMD-761 Datasheet, PDF (157/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
GART Cache Size
Bar1 + 0x08
31
30
29
28
27
26
25
24
Bit
GART_Cache_Size
Reset
0
0
0
0
0
0
0
0
R/W
R
23
22
21
20
19
18
17
16
Bit
GART_Cache_Size
Reset
0
0
0
0
0
0
0
0
R/W
R
15
14
13
12
11
10
9
8
Bit
GART_Cache_Size
Reset
0
0
0
0
0
0
0
0
R/W
R
7
6
5
4
3
2
1
0
Bit
GART_Cache_Size
Reset
0
0
0
1
0
0
0
0
R/W
R
Register Description
Bit Definitions
Bit Name
31–0 GART_Cache_Size
GART Cache Size (Bar1 + 0x08)
Function
GART Cache Size
The AMD-761™ system controller implements a GART table cache that contains 16 entries,
organized as eight-way set associative.
Programming Notes
Chapter 2
AMD-761™ System Controller Programmer’s Interface
145