AMD-761 Datasheet, PDF (210/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Delayed Transactions
and Target Latency
Enabled
2. A second PCI master requests the bus to access main
memory, and it receives a bus grant from the AMD-761
system controller PCI arbiter, but it must wait until the
memory read cycle initiated by the previous master is
completed. If this master’s cycle was targeted to another
PCI agent, it still could not begin the transaction because
the bus is tied up by the previous master and the AMD-761
system controller.
3. Some number of PCI clocks later, the memory subsystem
returns read data to the master completing the transaction.
The bus goes idle, so the next master begins its transaction.
This example assumes that a memory read transaction is
initiated by a PCI master and that the AMD-761 system
controller is unable to return data within the specified 32 PCI
clock latency.
1. The AMD-761 system controller latches the memory read
command and the address, and initiates a memory read to
the memory controller and simultaneously issues a probe to
the processor. The memory subsystem is unable to return
the data within 32 PCI clocks, so it asserts the STOP# signal
while TRDY# remains inactive. This action causes the
master that originated the cycle to disconnect, and it must
re-arbitrate for the bus. Meanwhile, the AMD-761 system
controller memory controller continues to process the
enqueued memory read transaction.
2. A second PCI master’s bus request is now granted.
• If the request is a read from main memory, the AMD-761
system controller retries the cycle but does not queue
the transaction because it already has an outstanding
delayed transaction in progress.
• If the request is to a peer PCI agent, then the transaction
can continue in parallel to the memory cycle being
completed by the AMD-761 system controller.
3. The original master wins bus arbitration and retries its read
command, and the AMD-761 system controller now
responds with the read data within the specified maximum
target read latency.
In summary, if compliance to the target latency rules is desired,
then it is recommended that delayed transactions enable and
the target latency bits are enabled.
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PCI Bus Interface
Chapter 5