AMD-761 Datasheet, PDF (63/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
DRAM Timing
31
30
29
28
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26
Bit SBPWaitState AddrTiming_A AddrTiming_B RD_Wait_State Reg_DIMM_En t_WTR
Reset
X
X
X
X
X
X
R/W
R/W
Dev0:F0:0x54
25
24
t_WR
X
X
23
22
21
20
19
18
17
16
Bit
t_RRD
Reserved
Idle_Cyc_Limit
Reset
X
0
0
0
0
X
X
X
R/W
R/W
R
R/W
15
14
13
12
11
10
9
8
Bit
PH_Limit
Reset
X
X
R/W
R/W
Reserved
0
0
R
t_RC
t_RP
X
X
X
X
R/W
7
Bit
t_RP
Reset
X
R/W
6
5
4
3
2
t_RAS
t_CL
X
X
X
X
X
R/W
1
0
t_RCD
X
X
Register Description
This register defines the DRAM timing parameters for all banks. BIOS software must set appropriate values in this register
before setting the SDRAM_Init bit (See “Bit Definitions DRAM Mode/Status (Dev0:F0:0x58)” on page 57) or attempting
any DRAM accesses.
Note that this register is not initialized at reset time, and all bits must be initialized by BIOS for proper operation. This
action should be done prior to attempting DRAM access.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
51