AMD-761 Datasheet, PDF (46/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions (Continued)
PCI Command and Status (Dev0:F0:0x04)
Bit Name
Function
7 STEP
Address Stepping
This bit is always 0 because the AMD-761™ system controller does not perform
address stepping.
6 PERR
Parity Error Response
This bit is always 0 because the AMD-761 system controller does not report data parity errors.
5 VGA
VGA Palette Snoop Enable
This bit is always 0, indicating that the AMD-761 system controller does not snoop the VGA
palette address range.
4 MWINV
Memory Write and Invalidate Enable
This bit is always 0 because the AMD-761 system controller does not generate memory
write and invalidate commands.
3 SCYC
Special Cycle
This bit is always 0 because the AMD-761 system controller ignores PCI special cycles.
2 MSTR
Bus Master Enable
This bit is always set, indicating that the AMD-761 system controller is allowed to act as a bus
master on the PCI bus.
1 MEM
Memory Access Enable
0 = PCI memory accesses ignored
1 = PCI memory accesses responded to
0 I/O
I/O Access Enable
This bit is always 0 because the AMD-761 system controller does not respond to I/O cycles
on the PCI bus.
Programming Notes
Table 7 lists the controls required to enable the assertion of the AMD-761 SERR# pin and the various status bits that can
be read to determine when the SERR# and A_SERR# pins have been asserted.
Table 7. AMD-761™ System Controller SERR# Assertion Control and Status Bits
SERR# Source
SERR# Pin
Assertion Control
GART or ECC error
Enabled by bit 8, Dev 0:F0:0x04, PCI
Status/Command register.
Enabled by bit 8, Dev 1:F0:0x04, PCI
A_SERR# assertion on AGP
Status/Command register, and bit 17,
interface forwarded to SERR# pin Dev 1:F0:0x3C, AGP/PCI Interrupt and
Bridge Control.
Signalled System
Error Status Bit
Read bit 30, Dev 0:F0:0x04, PCI
Status/Command register.
Read bit 30, Dev 1:F0:0x1C, AGP/PCI
Status, I/O and Base Limit, and bit 30,
Dev 1:F0:0x04, AGP/PCI
Command/Status.
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AMD-761™ System Controller Programmer’s Interface
Chapter 2