AMD-761 Datasheet, PDF (26/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Table 4. AMD Athlon™ Processor Special Cycle Encodings (Continued)
Special Cycle
STOP/GRANT
PCI Address and
Data Field
Contents
0012 0002
Processor Description
AMD Athlon™ processor generates in
response to assertion of the STPCLK.
WrLWs command: SysAddOut:
MSB=0 & [33:0] = 1 F8000 0000
SysDatOut: [31:0] = 0012 0002
Northbridge and Southbridge
Description
The AMD-761™ system controller waits
for all queues to memory to be empty
(assumes the PCI grant enable register
is clear, “Dev0:F0:0x84” on page 70).
The AMD-761 system controller system
controller optionally (via
“Dev0:F0:0x60” on page 61) initiates
an AMD Athlon processor system bus
disconnect to this specific processor.
The AMD-761 system controller
forwards onto the PCI bus (after the
optional system bus disconnect) PCI
special cycle command: AD[31:0] =
0012 0002 (address and data).
The AMD-766™ peripheral bus
controllers receives and enters the
appropriate power state. The
AMD-766 peripheral bus controllers
may then assert DCSTOP# to the
Northbridge to signal that it should
deassert CKE to DDR SDRAMs and
stop its internal clocks.
14
AMD-761™ System Controller Programmer’s Interface
Chapter 2