AMD-761 Datasheet, PDF (165/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Chapter 3
When the DIMM socket sides are equally sized, the order of
address space programming between them is not important.
Each side/row/bank of DRAM requires 4 bytes as previously
stated. The patterns that satisfy the Address Mask and Base
Address for various sizes of sides/rows/banks are shown in
Table 19.
Table 19. Memory Size Addresses
Bank / Row Size
Address Mask
Base Address
[Address Lines]
8 Mbytes
16 Mbytes
32 Mbytes
64 Mbytes
128 Mbytes
256 Mbytes
512 Mbytes
1024 Mbytes (1 Gbyte)
2048 Mbytes (2 Gbytes)
[31:23]
N/A
N/A
0000_0001_1
0000_0011_1
0000_0111_1
0000_1111_1
0001_1111_1
0011_1111_1
0111_1111_1
[31:23]
0000_0000_1
0000_0001_0
0000_0010_0
0000_0100_0
0000_1000_0
0001_0000_0
0010_0000_0
0100_0000_0
1000_0000_0
The address mask and base address bits are presented as
xxxx_xxxx_x to show correspondence with address lines. In
practice, the 9 bits of address mask map to bank n, bits 15:7
and the 9 bits of base address map to bank n, bits 31:23.
The minimum memory size or granularity for DDR is 32
Mbytes. However, all base address and address mask bits
represent a granularity of 8 Mbytes.
The symmetry of the DDR device—that is, organization of
storage elements rows and columns—dictates the addressing
mode configuration. The specified addressing mode dictates
the physical mapping of the memory address signals to the
DDR device address signals. The addressing modes of the
AMD-761 system controller memory controller map to industry-
standard DDR device symmetries set forth by the Joint
Electron Device Engineering Council (JEDEC). Therefore, the
addressing mode is set according to the devices on the DIMM.
„ Addr_Mode => 01b for 64-Mbit and 128-Mbit DRAMs
„ Addr_Mode => 10b for 256-Mbit and 512-Mbit DRAMs
DDR SDRAM Interface
153