AMD-761 Datasheet, PDF (193/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
SW_Cal_Dly value by performing a manual window detection
rather than using the specified values.
Manual window detection can be accomplished with the
following steps:
„ Disable the PDL auto-calibration feature by setting Dev
0:F1:0x40, bit [5] = 1b0. Disabling auto-calibration prevents
auto-calibration interference while BIOS manipulates this
process manually.
„ Determine the operating range of each PDL by adjusting
each PDL tap from minimum to maximum to determine the
data window range. This determination is accomplished by
multiple iterative writes to alter the PDL and reading back
"expect" data from DDR memory after each PDL tap is
altered. For x8/x16 devices, this process is performed at the
byte resolution. For x4 devices, this process is performed at
the nibble resolution. The Actual Delay is adjusted via Dev
0:F1:0x44, bits [7:0] through Dev 0:F1:0x88, bits [7:0]. After
the Actual Delay is configured, BIOS must write a 1b to the
Use Actual Delay bit (Dev 0:F1:0x40, bit [6]) to apply the
new Actual Delay value.
„ Once the operational range for each byte (for x8/x16
devices) or for each nibble (for x4 devices) is determined,
the center point for this window can be determined by
dividing these ranges by two, which yields the “target
window PDL tap.”
„ The average PDL tap value must be determined for
knowledge of the expected delay per tap of the PDL. This
value can be retrieved by performing a software-initiated
calibration. First set the Actual Delay Update Inhibit Dev
0:F1:0x40, bit [4] to a 1b to prevent a calibration update.
Initiate a calibration by writing a 1b to Dev 0:F1:0x40, bit
[7], and then polling this bit to become a 0b to determine
when the calibration is complete. The total number of PDL
taps that make up 5 ns (for 100-MHz operation) or 3.75 ns
(for 133-MHz operation) can be found in the Clock Delay
field for each calibrator in Dev 0:F1:0x44, bits [31:24],
through Dev 0:F1:0x88, bits [31:24]. By dividing the
appropriate period (as applies to the frequency of the
AMD-761 system controller) by the values found in the
Clock Delay fields yields the “average delay per PDL tap.”
Chapter 3
DDR SDRAM Interface
181