AMD-761 Datasheet, PDF (176/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Address Timing for
Copy-A
Super Bypass Wait
State
This bit assumes A bus and B chip-select DIMM socket mapping
is such that the B bus uses Chip Select bit [7:6] and [3:2]. This
motherboard mapping should be adhered to should BIOS want
to control the A bus and B bus HOLD timing separately. Refer
to Table 27 on page 165 for typical settings.
The address timing for Copy-A bit (Dev 0:F0:0x54, bit [30])
specifies additional HOLD time for the address and command
bus A. When this bit is set to 1b, the memory address bus
(MAA[14:0]), RASA#, CASA#, WEA#, CKEA, and CS[5:4 and
1:0]# is delayed an additional 350 ps (best case) and 600 ps
(worst case) to provide additional HOLD time to the DDR
device. This bit should be set by BIOS when registered DIMMs
are installed and set to 0b when unbuffered DIMMs are
installed.
This bit assumes A bus and B chip-select DIMM socket mapping
is such that the B bus uses Chip Select bit [5:4] and [1:0]. This
motherboard mapping should be adhered to should BIOS want
to control the A bus and B bus HOLD timing separately. Refer
to Table 27 on page 165 for typical settings.
The Super Bypass Wait State bit (Dev 0:F0:0x54, bit [31])
specifies an additional one system clock wait state for super
bypass requests, when set to 1b. A super bypass cycle is a low-
latency request to DDR memory from the bus interface unit
when all reordering queues are empty. This super bypass cycle
allows direct access to DDR memory. For internal timing
reasons, this bit must be set for 133-MHz operation. This bit
should be set to 0b for 100-MHz operation or below. Refer to
Table 27 for typical settings.
164
DDR SDRAM Interface
Chapter 3