AMD-761 Datasheet, PDF (180/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
DIMM Clock Disable
Table 28.
Value
00
01
10
11
Refresh Rate
66 MHz
30.72 µs
23.04 µs
15.36 µs
7.68 µs
100 MHz
20.48 µs
15.36 µs
10.24 µs
7.68 µs
133 MHz
15.36 µs
11.52 µs
7.68 µs
3.84 µs
The DIMM clock disable bits (Dev 0:F0:0x58, bits [31:26])
provide a way to individually disable the six differential DDR
clock pairs provided for the DDR DIMMs. After BIOS memory
sizing, these bits can be used to disable clocks to empty DDR
DIMM slots. The setting of a bit disables the corresponding
clock pair. Each clock pair is connected according to the
motherboard layout for registered or unbuffered DIMMs. Refer
to the appropriate motherboard schematic to verify DDR clock
DIMM mapping to a particular DIMM slot.
With a system hard reset, these bits are cleared, thus enabling
all clock pairs. Because an AMD-761 system controller system
reset is issued during a power-managed S3 state, all clocks are
re-enabled following the exit from this state. Therefore, BIOS
should return to this register and restore the disabled clock
pairs that it had previously disabled during POST.
Note: DDR clocks are automatically disabled during the S3 power-
managed state when unbuffered DIMMs are installed but
continue running an additional six clocks when registered
DIMMs are installed.
168
DDR SDRAM Interface
Chapter 3