AMD-761 Datasheet, PDF (230/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Registers
-----
Bits
0x0x0x54h
Description
SDRAM Timing
t_RAS = Minimum Bank Active
6:4 ^Time
SPD # 30
t_CL = CAS Latency
3:2
SPD # 25 or
# 23 or
#9
1:0
t_RCD — RAS to CAS Latency
SPD # 29
Initialized/
Required
Value
Actual
Value
Key fcn( )
Notes
000 = 2 cyc, 001 = 3 cyc
FSB 010 = 4 cyc, 011 = 5 cyc
xxxb
B and 100 = 6 cyc
SPD 101 = 7 cyc (safe)
110 = 8 cyc, 111 = 9 cyc
FSB
00 = 3 cyc (optional on
DIMM, not recommended)
xxb
B and _{01 = 2 cyc, recommended}
SPD _{10 = 2.5 cyc, 11-reserved}
FSB
00 = 1 cyc, 01 = 2 cyc
xxb
B and _{10 = 3 cyc (safe), 11 = 4 cyc}
SPD
KEY:
B= Mandatory BIOS function
A= AGP setup by BIOS
c = Calculated/set by AMD-761™ internal logic
P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS
r = Hardcoded and reserved
u = PCI operational user interface E = Elective BIOS function
7.1.1
Example Settings for Memory Timing
The table below provides example BIOS settings for the DRAM
Timing register, for both 100-MHz and 133-MHz bus speeds.
Note some register bits change based on the DIMM type:
„ U for Unbuffered DIMMs
„ R for registered DIMMs
Note also that SPD values observed to date are from production
DIMMs. Future additions and changes to the SPD bytes should
be expected.
218
Recommended BIOS Settings
Chapter 7