AMD-761 Datasheet, PDF (5/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
5 PCI Bus Interface
195
5.1 Delayed Transactions and Ordering Rules Usage . . . . . . . 195
5.1.1 Delayed Transactions and Target Latency . . . . . . . . 196
5.1.2 Transaction Ordering Rules . . . . . . . . . . . . . . . . . . . . 199
5.1.3 Special Arbitration Considerations
for the Southbridge . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.2 PCI Performance Optimization Options . . . . . . . . . . . . . . . . 202
5.2.1 Read Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.2.2 PCI Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
5.2.3 PCI Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6 AGP Interface
205
6.1 AGP Dynamic Compensation Requirements . . . . . . . . . . . . 205
6.1.1 The AGP 4X Dynamic Compensation Register . . . . . 206
6.1.2 Selection of 1.5- or 3.3-V AGP Signalling . . . . . . . . . . 207
6.2 Feature Override Bits for AGP Cards . . . . . . . . . . . . . . . . . 208
6.3 BIOS Initialization Requirements . . . . . . . . . . . . . . . . . . . . 209
6.4 AGP Miniport Driver Requirements . . . . . . . . . . . . . . . . . . 210
7 Recommended BIOS Settings
211
7.1 PCI Bus 0, Device 0, Function 0 Registers . . . . . . . . . . . . . 212
7.1.1 Example Settings for Memory Timing . . . . . . . . . . . . 218
7.1.2 Examples: AGP Compensation Register Settings
(0xB4-0xBB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.1.3 PCI Bus 0, Device 0, Function 1 Registers . . . . . . . . . 236
7.2 PCI Bus 0, Device 1, Function 0 Registers . . . . . . . . . . . . . 246
Table of Contents
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