AMD-761 Datasheet, PDF (129/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
2.4.5
Table 15.
Device 1: PCI-to-PCI Bridge Configuration Registers
The registers defined in this section are required to implement
the PCI-to-PCI bridge function (device 1) in the AMD-761
system controller Northbridge. In Table 15, the column entitled
Offset consists of the register number specified in the
Configuration Address register bits [7:2] concatenated with
0b00 to form a simple 1-byte offset.
Device 1 Configuration Register Map
PCI-to-PCI Bridge (Device 1)
Device ID
Vendor ID
Status
Command
Class Code0x0600
Reserved
SecLatency
Time
Header Type
Primary Latency
Timer
Reserved
Subordinate Bus Secondary Bus
Num
Num
Secondary Status
I/O Limit
Revision ID
Reserved
Primary Bus
Num
I/O Base
Memory Limit
Memory Base
Prefetchable Memory Limit
Prefetchable Memory Base
Reserved
I/O Limit Upper 16 Bits
I/O Base Upper 16 Bits
Reserved
Bridge Control
Interrupt
Pin
Reserved
Interrupt
Line
Miscellaneous Device 1 Control
Reserved
Offset
0x00
0x04
0x08
0x0C
0x10 to 0x17
0x18
0x1C
0x20
0x24
0x28 to 0x2F
0x30
0x34 to 0x3B
0x3C
0x40
0x44 to 0xFF
Reference
“Dev1:0x00” on
page 118
“Dev1:0x04” on
page 120
“Dev1:0x08” on
page 123
“Dev1:0x0C” on
page 124
“Dev1:0x18” on
page 125
“Dev1:0x1C” on
page 127
“Dev1:0x20” on
page 130
“Dev1:0x24” on
page 132
“Dev1:0x30” on
page 134
“Dev1:0x3C” on
page 135
“Dev1:0x40” on
page 137
Chapter 2
AMD-761™ System Controller Programmer’s Interface
117