AMD-761 Datasheet, PDF (161/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
3 DDR SDRAM Interface
This chapter details BIOS configuration as it pertains to the
AMD-761™ system controller DDR SDRAM controller. The
topics discussed in this chapter are entitled as follows:
„ DDR DIMMS and DDR SDRAMs on page 150
• DDR Speed Grades on page 150
• DDR DIMM Data from Serial Presence Detect (SPD)
Device on page 151
„ Memory Space Configuration on page 152
„ DDR Memory DIMM Timings on page 157
„ Additional Memory Controller Settings on page 161
„ DRAM Mode/Status Settings on page 165
„ ECC and Memory Scrubbing on page 169
„ Programmable Delay Lines (PDL) on page 174
„ DDR I/O Drive Strength on page 182
3.1 Overview
To date, there are two types of DDR memory DIMMs—
unbuffered and registered. The AMD-761 system controller can
be configured to support up to two unbuffered DIMM slots with
two banks each, or up to four registered DIMM slots with two
banks each. Registered and unbuffered implementations
cannot be intermixed.
The AMD-761 system controller embeds the DDR SDRAM
memory controller of the system. All programming registers
that configure the memory controller reside in PCI
configuration space. This space is defined in Bus 0, Device 0,
and exists in both Function 0 and Function 1.
Motherboard and Northbridge characteristics are programmed
from data provided by the respective designers and
manufacturers. This data includes bus speed implementations,
memory bus signal strengths and slew rates, and internal
memory controller characteristics, etc.
Chapter 3
DDR SDRAM Interface
149