AMD-761 Datasheet, PDF (178/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
SDRAM Initialization
Mode Register Status
AMD-761 system controller provides a data width selection for
each chip select, although it is unlikely that a double banked
DIMM can support x4 devices on one side and x8/x16 devices
on the other. However, this resolution is provided to allow chip-
select signal routing flexibility on the motherboard should the
same DIMM socket not use neighboring chip-select wiring.
The SPD byte 13 provides DDR device data width information
and can be used to set these bits accordingly.
The SDRAM Initialization bit (Dev 0:F0:0x58, bit [25]), when
written to a 1b, initiates the DDR device initialization
sequence. However, as mentioned below, the Suspend to RAM
bits (Dev 0:F0:0x58, bits [22:21]) must be written to a 01b in
order for the initialization sequence to occur. The BIOS should
first initialize the DDR timing control registers and drive
strength registers prior to setting this bit. This bit remains set
after the initialization sequence has completed. Status as to
the completion of the initialization sequence can be provided
by polling the Mode Register Status (Dev 0:F0:0x58, bit [23])
but only after setting the Mode Register Status bit. This
procedure is described below. The SDRAM Initialization bit is
reset to 0b during a Suspend To RAM because a system reset is
issued in this case.
The Mode Register bit (Dev 0:F0:0x58, bit [23]), when written
with a 1b, is used to initiate a Load Mode Register command to
the DDR devices. The Load Mode Register command programs
the CAS latency of the device, burst length, and burst order.
The burst length and burst order are fixed to a burst of eight
and the device is programmed for interleaved mode. However,
the CAS latency is configurable via the CAS Latency bit. BIOS
must set the CAS latency bit to its correct value (defined by
DDR devices specification and operating frequency) before the
Mode Register bit is set. This bit is then cleared by the
AMD-761 system controller memory controller after the load
mode register cycle is issued to the DDR devices. Therefore,
after setting this bit, BIOS should poll this bit until it becomes
0b to verify that the Load Mode Register command has been
applied to the DDR devices before continuing. The
recommended method is to set this bit (after already
initializing the CAS Latency bit) when writing to this register
to set bits [22:21] of this register to a 01b and bit 25 of this
register to a 1b. Because the DDR initialization has priority
166
DDR SDRAM Interface
Chapter 3