AMD-761 Datasheet, PDF (221/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
6.3
BIOS Initialization Requirements
This section lists the steps in an algorithm recommended to
properly configure the AMD-761 system controller AGP fast
write and rate features, as well as the compensation and slew
rate values.
This BIOS algorithm must properly detect the AGP card’s
signalling type (1.5 V or 3.3 V) and enable the appropriate
features as listed in the steps below. Note that these steps are
require before the AGP interface is enabled.
1. Detect the signalling level (1.5 V or 3.3 V) by reading the
value of the TYPEDET# pin that was latched by the
AMD-761 system controller at reset. This value can be read
in the Configuration Status register, Dev 0:F0:0x88, bit 25.
• If 0, then 1.5-V signalling is selected by the AGP card. If
1, then 3.3-V signalling is used.
2. Configure the override bits according to the signalling level
as listed in Table 34 on page 210 and the following notes.
• If 1.5 V, then the 4X_Override bit should be cleared, and
the FW_Enable bit should be set in the AGP 4X Dynamic
Compensation register (Dev 0:F0:0xB4, bits 6 and 7,
respectively). This action causes the AGP Status register
(Dev 0:F0:0xA4) to report 4X and fast write capability to
the operating system.
• If 3.3 V, then the 4X_Override bit should be set, and the
FW_Enable bit should be cleared in the AGP 4X
Dynamic Compensation register (Dev 0:F0:0xB4, bits 6
and 7, respectively). This action causes the AGP Status
register (Dev 0:F0:0xA4) to report a maximum rate of 2X,
and no fast write capability to the operating system.
3. Program the appropriate compensation, drive strength,
bypass, and slew rates to the AGP I/O pads in the AGP 4X
Dynamic Compensation and AGP Compensation Bypass
register according to Table 34 below.
Chapter 6
AGP Interface
209