AMD-761 Datasheet, PDF (202/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
4.4
simply enables its clock trees and reconnects the processor.
Because no power is removed from the system, and the RESET#
signal is not asserted, all AMD -7 61 syst em c ontroller
configuration registers retain their original value prior to
entering the S1 state.
The S1 sleep state requires specific configuration registers in
the AMD-768 peripheral bus controller or AMD-766 peripheral
bus controller to be initialized for proper generation of the
STPCLK# and DCSTOP# signals and resume events.
S3 Suspend to RAM State Requirements
The ACPI S3 state achieves maximum power savings and low-
latency resume by shutting off most system power supplies
while retaining system context in DRAM. This action requires
that the AMD-761 system controller core voltage remain
powered on along with the DRAM and part of the Southbridge,
while the remaining platform components are powered off.
For any system enabling the S3 state, a number of core logic
PCI configuration registers and processor MSRs must be saved
or restored prior to suspending or restoring S3. Also, certain
hidden bits must be unmasked. These requirements apply to all
platforms regardless of segment and whether or not AMD
PowerNow!™ is used.
To the AMD-761 system controller, the configuration register
initialization required for S3 support is the same as that
required for S1 support. The AMD-761 system controller
requires the following of the BIOS/drivers for S3 support:
„ The Stp_Grant_Discon_En must be set in the BIU
Status/Control register. When this bit is set, the AMD-761
system controller flushes internal queues after receiving
the Stop Grant special cycle, force the DDR DRAM into self-
refresh mode, and forward the Stop Grant special cycle to
the PCI bus to the Southbridge.
„ DRAM refresh must be enabled by writing a 0 to the
Ref_Dis test bit in the DRAM Mode/Status register (Dev
0:F0:0x58, bit 19).
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Power Management
Chapter 4