AMD-761 Datasheet, PDF (211/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
5.1.2
Transaction Ordering Rules
The PCI Local Bus Specification, Revision 2.2, defines various
transaction ordering rules to accommodate the producer-
consumer model and to prevent deadlock conditions on the bus
under certain conditions.
The AMD-761 system controller provides the ability to
optionally disable strict adherence to the transaction ordering
rules if desired. The ordering rules are defined such that data
and its associated flags are visible by any agent on any segment
of the PCI bus. In typical systems, however, this visibility is not
necessary, as both data and flags typically reside in main
system memory. It may be possible to achieve slightly better
PCI bus performance when ordering rules compliance is
disabled, because PCI masters attempting to read main
memory are not disconnected to force the flushing of posted
write FIFOs in the AMD-761 system controller.
Figure 6 on page 201 illustrates an example system
implementation with data and associated flags stored in
different locations. In this example, the flag is stored in main
memory (DRAM) and the data is stored in the PCI agent.
The sections that follow describe the behavior in a system with
and without ordering rules compliance.
With Ordering Rules
Enabled
Using Figure 6 as an example, the following case describes the
behavior of the AMD-761 system controller when ordering
rules are followed.
1. The processor writes data (memory write) destined to an
agent on the PCI bus, and the data is posted in the AMD-761
system controller PCI posting buffer.
2. The processor then sets a flag in memory, informing the PCI
agent that the data is written.
3. The PCI master reads the flag, but this action causes the
data previously written by the processor to be flushed from
the AMD-761 system controller posted write buffer. The PCI
master is disconnected by the AMD-761 system controller
(STOP# active with TRDY# inactive) to allow the AMD-761
system controller to write the data to the PCI agent.
Chapter 5
PCI Bus Interface
199