AMD-761 Datasheet, PDF (77/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31 Clk_Fwd_Offset
30–29 Data_Init_Cnt
28–27 Addr_Init_Cnt
26–24 Sys_Data_Even
_Clk_Dly
23–21 Sys_Data_Odd
_Clk_Dly
20–19 Sys_Data_Even
_Dly
18–17 Sys_Data_Odd
_Dly
16–15 Sys_Addr_Dly
14–11 SysDC_Dly
10–8 Sys_Addr_Clk
_Dly
7–6 Sys_Rst_Clk
_Offset
5–3 Sys_Data_Rec
_Mux_PreLd
2–0 Sys_Addr_Rec
_Mux_PreLd
Programming Notes
BIU0 SIP (Dev0:F0:0x64)
Function
Clock Forward Offset
0 = The AMD-761™ system controller delays driving of the data and clock for
AMD Athlon™ processor system bus SysData bits [31:16] and [63:48] by ~1000 ps.
1 = All AMD Athlon system bus ClkFWD groups drive the same nominally SysClk edge.
Data Initialization Count
This value specifies the number of SysClks from the launch of data by the processor until it
can be read from the AMD-761 system controller receive FIFO.
Address Initialization Count
This value specifies the number of SysClks from the launch of a command by the
processor until it can be read from the AMD-761 system controller receive FIFO.
System Data Even Clock Delay -- AMD Athlon processor SIP[33:31]
This value specifies the number of processor XICLK phases between the nominal start of
bit time and the launch of the even clocks.
System Data Odd Clock Delay -- AMD Athlon processor SIP[30:28]
This value specifies the number of processor XICLK phases between the nominal start of
bit time and the launch of the odd clocks.
System Data Even Delay -- AMD Athlon processor SIP[27:26]
This value specifies the number of processor XICLK phases between the nominal start of
bit time and the launch of the even data (SysData bits [31:16] and [63:48]).
System Data Odd Delay -- AMD Athlon processor SIP[25:24]
This value specifies the number of processor XICLK phases between the nominal start of
bit time and the launch of the odd data (SData bits [15:00] and [47:32]).
System Address Delay -- AMD Athlon processor SIP[23:22]
This value specifies the number of processor XICLK phases between the nominal start of
bit time and the launch of the address (SysAddOut).
SysDC Delay -- AMD Athlon processor SIP[19:16]
This value is an internal processor parameter that is used to cause SYSDC commands and
their associated data to arrive in the processor core at the correct relative times.
System Addr Clock Delay -- AMD Athlon processor SIP[13:11]
This value specifies the number of processor XICLK phases between the nominal start of
bit time and the launch of the SADDOUTCLK.
System Reset Clock Offset -- AMD Athlon processor SIP[10:9]
This value is an internal processor parameter that is used to properly time AMD Athlon
system bus data transfer.
System Data Rec Mux PreLd -- AMD Athlon processor SIP[8:6]
This value specifies the number of SysClk phases from the launch of data by the AMD-761
system controller until it can be read from the AMD Athlon receive FIFO.
System Address Rec Mux PreLd -- AMD Athlon processor SIP[5:3]
This value specifies the number of SysClk phases from the launch of address/command by
the AMD-761 system controller until it can be read from the AMD Athlon receive FIFO.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
65