AMD-761 Datasheet, PDF (168/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Chip Select Enable
Example: Memory
Base Address
Registers
The Chip Select Enable bit (Dev 0:F0:0xC0, bit [0] through Dev
0:F0:0xDF, bit [0]) specifies whether a bank of memory exists
for that corresponding chip select. When enabled with a 1b, the
incoming address is eligible to be compared with bits [31:23]
and [15:7] for chip-select decode. A 0b in this field disables the
associated chip select, thus the associated Base Address Chip
Select and Address Mask fields are ignored.
Table 22 is an example of how to size the Memory Base register
for a total of 128 Mbytes using a two-bank DIMM at 64 Mbytes
per bank.
Table 22. Memory Sizing Example, 128 Mbytes Total
Registers – Bus:00 Device:00 Function:00
0 1 2 3 4 5 6 7 8 9 ABCDE F
C 83 03 00 00 83 03 00 04 00 00 00 00 00 00 00 00
D 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
For the purpose of illustrating memory sizing, the bytes 0xC0–
0xDF are the relevant bytes. Configuration bytes C0h, C1h,
C2h, and C3h are for Bank 0. Byte C0h contains bits [7:0], C1h
bits [15:8], etc. This example shows 64 Mbytes in both banks 0.
Configuration bytes C4h, C5h, C6h, and C7h are for bank 1
Bits C0h[7] and C1h[7:0] contain the Address Mask for 64 Mbytes.
Bits C4h[7] and C5h[7:0] contain the Address Mask for 64 Mbytes.
Bit C0h[0] and bit C4h[0] signal Bank Enable.
Bit C2h[7] and bits C3h[7:0] set a Base Address of 0 Mbyte for
side/row/bank 0.
Bit C6h[7] and bits C7h[7:0] set a Base Address of 64 Mbytes
for side/row/bank 1.
The total memory size is 128 Mbytes. Banks 2–7 are empty. The
relevant bytes are set to 0.
156
DDR SDRAM Interface
Chapter 3