AMD-761 Datasheet, PDF (201/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
4.3
S1 Power-On Suspend State Requirements
The ACPI S1 state uses the Southbridge DCSTOP# signal to
gate off the AMD-761 system controller’s internal clock trees
for a very low-power state. All voltages remain powered on in
this mode.
To the AMD-761 system controller, the configuration register
initialization required for S1 support is the same as that
required for C2 support as described in Section 4.1 on
page 186. The AMD-761 system controller requires the
following BIOS/drivers for S1 support:
„ The Stp_Grant_Discon_En must be set in the BIU
Status/Control register. When this bit is set, the AMD-761
system controller flushes internal queues after receiving
the Stop Grant special cycle, forces the DDR DRAM into
self-refresh mode, and forwards the Stop Grant special cycle
to the PCI bus to the Southbridge.
„ DRAM refresh must be enabled by writing a 0 to the
Ref_Dis test bit in the DRAM Mode/Status register (Dev
0:F0:0x58, bit 19).
„ Self-refresh must be enabled by writing a 1 to the
Self_Ref_En bit in the Status/Control register (Dev
0:F0:0x70, bit 18).
„ To ensure that no probes are generated, all PCI/AGP traffic
must be prevented by the peripheral software drivers before
entering the S1 state when DCSTOP# is asserted. It is
expected that the drivers have already placed each PCI/AGP
peripheral into the D3 state prior to STPCLK# assertion by
the Southbridge.
The S1 state is supported by the AMD-761 system controller for
both unbuffered and registered DDR DIMMs. However, when
registered DIMMs are installed in the system (according to the
Reg_DIMM_En bit in the DRAM Timing register in Dev
0:F0:0x54), the DRAM clocks (CLKOUT[5:0], CLKOUT[5:0]#)
continue to be driven active. This action is required because
the registered DIMMs do not support removal of the clock
input unless in reset.
The S1 sleep state has a very low resume latency because the
PLLs are already running. The AMD-761 system controller
Chapter 4
Power Management
189