AMD-761 Datasheet, PDF (205/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Resume from S3/S4/S5 or mechanical off states,
RESET# asserted, forces 00
Resume from S3 state, BIOS writes 1X
• DRAM CKE pins are Low, all DRAM
CLKOUT pins are enabled
STR_Control
00
Resume from S4/S5 or mechanical
off states, BIOS writes 01
STR_Control
1X
Powerdown or enter S3 state,
STR_Control bits reset to 00
by assertion of RESET# pin
STR_Control
01
• AMD-761™ system controller asserts DRAM CKE pins and exits
self-refresh mode.
• The AMD-761 system controller retains the value of all memory
controller configuration registers; all other registers are cleared
to their power-up values.
• BIOS disables any unused DDR clocks.
• BIOS can now begin restoring all other configuration registers
from DRAM.
• DRAM CKE pins are asserted by the AMD-761 system controller.
• BIOS initiates the AMD-761 system controller to start DRAM.
power-up initialization process, including disabling any unused
DDR clocks, writing to DRAM mode registers, etc.
• BIOS continues normal system initialization and POST process.
Figure 5. Suspend to RAM (STR_Control) Bits Usage
4.5 Clock Throttling
Clock throttling is a power management mechanism that
periodically causes the assertion of the STPCLK# signal to the
processor to achieve lower system power. Clock throttling can be
accomplished through a combination of hardware and software
and can be performed at regular intervals—that is, modulating
the STPCLK# pin or through a more sophisticated system such
as implementing thermal sensors on the motherboard.
The AMD-761 system controller supports clock throttling with
the same hardware mechanisms that are used for C2 support
and requires the following BIOS configuration register
initialization.
„ The Stp_Grant_Discon_En must be set in the BIU
Status/Control register. When this bit is set, the AMD-761
system controller flushes internal queues after receiving
the Stop Grant special cycle, forces the DDR DRAM into
Chapter 4
Power Management
193