AMD-761 Datasheet, PDF (163/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
3.2.2
Chapter 3
specific and based on the operating frequency of the device.
The CAS latency is specified as the initial latency (in clocks)
required by the device before data is returned during a read
access. In general, the higher the frequency, the larger the CAS
latency value. Typical device CL parameters and their
respective frequencies are shown in Table 17.
Table 17. Typical CL Parameter Settings for PC1600 and PC2100
Designation
PC1600
PC2100
CAS Latency (CL) Setting
2
2.5
DDR Memory Clock Speed
100 MHz
133 MHz
Note: CAS latency settings are valid only if an acceptable entry
for the corresponding bus speed exists in SPD byte 9 or 23.
DDR DIMM Data from Serial Presence Detect (SPD) Device
DDR memory systems implemented with the AMD-761 system
controller require use of the Serial Presence Detect (SPD)
data. This data describes configuration and speed
characteristics of the DDR DIMM and DDR SDRAM devices
mounted on the DIMM. The SPD is a serial EEPROM that
physically exists on the DIMM and is encoded by the DIMM
manufacturer. A description of this EEPROM is usually
provided on a data sheet for the DIMM itself along with data
describing the memory devices (chips) used. The data sheet
should also contain the byte values for the DIMM encoded in
the SPD on the DIMM. The SPD is accessed via the I²C bus
implemented on the motherboard, normally via registers in a
Southbridge agent. Subroutines to access SPD data must be
provided in the BIOS or other code that requires access.
The I²C bus addresses the SPD via a 7-bit address where
convention dictates that memory DIMMs respond to an address
range beginning with 0xA0. The second memory DIMM
responds to 0xA2 and so on.
The I²C bus specification describes a 7-bit address. However,
this scheme actually uses 8 bits. The 8th bit is actually bit 0.
The scheme defines bit 0 as the read/write designation of the
address. Bit 0 equal to 0 means that the host is executing a
WRITE to the address. Bit 0 equal to 1 means that the host is
executing a READ from the address. Reality then is that A1
addresses a read operation to DIMM slot #0. A3 addresses a
DDR SDRAM Interface
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