AMD-761 Datasheet, PDF (111/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31–8 Reserved
7 SW_Recal
6 Use_Act_Dly
5 Auto_Cal_En
DDR PDL Calibration Control (Dev0:F1:0x40)
Function
Reserved
Software Recalibration
Software should write a 1 to this bit to cause recalibration of the PDLs. The hardware
recomputes the Cal_Delay values for all PDLs, based on the values of their SW_Cal_Dly
fields.
Status of the recalibration that was initiated by writing a 1 to this bit is also indicated in this
bit. After setting this bit, software should poll this bit until it becomes a 0 again.
0 = Calibration complete (default)
1 = Calibration not complete
If Auto_Cal_En is set, writes to this bit are ignored.
Also refer to Table 13, “PDL Calibration Modes,” on page 100.
Note: This bit should not be set if the system clock frequency is 66 MHz.
Use Actual Delay
Software should set this bit to indicate to the hardware that it has written to the Act_Dly
fields and wants to update the PDLs (all 18) with the newly written Act_Delay values.
Software only needs to change the Act_Delay values that are not currently at their desired
values (the other Act_Dly values are simply re-applied). This method should be used only
when SW_Recal and Auto_Cal_En bits are not set.
If Auto_Cal_En is set, writes to this bit are ignored.
Also refer to Table 13, “PDL Calibration Modes,” on page 100.
This bit always returns a 0 when read.
Auto Calibration Mode
0 = Auto-calibration mode off (default)
1 = Auto-calibration mode on
When this bit is set, all of the Cal_Dly values are recomputed periodically (according to the
setting of the Auto_Cal_Period field) for all PDLs, based on the values of their SW_Cal_Dly
fields. If the Act_Dly_Inh bit is not set, the Cal_Dly values are also applied to the Act_Dly.
Also refer to Table 13, “PDL Calibration Modes,” on page 100.
Note:
Once Auto_Cal_En is set to 1, clearing it makes the bit a 0, but the Auto-Calibration
logic may perform one more update, depending on when the Auto_Cal_En bit is
cleared. Therefore, BIOS should at least wait for the amount of time specified by
the Auto_Cal_Period field after clearing the Auto_Cal_En bit before attempting to
change any of the PDL parameters.
Note: This bit should not be set if the system clock frequency is 66 MHz.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
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