AMD-761 Datasheet, PDF (191/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Auto_Cal_En
Act_Dly_Inh
Auto_Cal_Period
Clk_Dly
Chapter 3
The Auto Calibration Enable bit (Dev 0:F1:0x40, bit [5])
provides a way for BIOS to enable the PDL auto calibration
function. When this bit is set, all of the Cal_Dly values are
recomputed periodically (according to the setting of the
Auto_Cal_Period field) for all PDLs, based on the values of
their SW_Cal_Dly fields. If the Act_Dly_Inh bit is not set, the
Cal_Dly values are also applied to the Act_Dly.
Note: Once Auto_Cal_En is set to 1, clearing it makes the bit a 0,
but the auto-calibration logic may perform one more
update, depending on when the Auto_Cal_En bit is cleared.
Therefore, BIOS should at least wait for the amount of time
specified by the Auto_Cal_Period field after clearing the
Auto_Cal_En bit before attempting to change any of the
PDL parameters.
Note: This bit should not be set if the system clock frequency is
66 MHz.
The Actual Delay Update Inhibit bit (Dev 0:F1:0x40, bit [4])
provides a way for BIOS to inhibit an auto-calibration value
from updating the PDLs. The setting of this bit affects both
auto-calibration and software-initiated calibration but not the
Use_Act_Dly method. After an exit from self-refresh, the
setting of this bit determines whether the Act_Dly value is
updated or not.
Note: The internal logic tests this bit just prior to updating the
Act_Dly, so the other bits in this register should be taken
into consideration when writing to this bit.
The Auto-Calibration Period (Dev 0:F1:0x40, bits [1:0]) bits
specify how often an auto-calibration occurs. The auto-
calibration periods are as follows:
„ 00 = 10000 system clocks
„ 01 = 1000000 system clocks
„ 10 = 10000000 system clocks
„ 11 = Reserved
BIOS should configure this field before setting the
Auto_Cal_En bit. This field should not be altered while
Auto_Cal_En is set.
The auto-calibrator’s Clock Delay (Dev 0:F1:0x44, bit [31:24]
through Dev 0:F1:0x88, bits [31:24]) is read-only and provides
DDR SDRAM Interface
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