AMD-761 Datasheet, PDF (164/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
3.3
read operation to DIMM slot #1. A0 addresses a write operation
to DIMM slot #0.
Memory Space Configuration
A DIMM may have one or two sides populated with DDR
devices. The term bank refers to one logical side of the DIMM
memory. For the purpose of this document, each bank has a
corresponding chip select. It is important to point out that
double-sided DIMMs require two separate chip-select signals.
Therefore, for these types of DIMMs, two separate base address
chip-select registers must be programmed. The size of each
bank is read from SPD, byte 31. The number of banks on the
DIMM is read from SPD byte 5.
The AMD-761 system controller DDR SDRAM controller
requires 21 bits of configuration information for each chip
select—that is, each side of the DIMM. These 21 bits are within
a full 32-bit configuration register that contains 11 reserved
bits. Usage of the 32 bits is shown in Table 18 and explained in
further detail below.
As previously mentioned, a DIMM socket may be single banked
(containing one logical side of DDR SDRAM devices) or double
banked (containing two logical sides of DDR SDRAM devices).
The DIMM socket may also be empty. If one bank is not present
or if the socket is empty—that is, two banks not present—then
their corresponding enable bit shown in Table 18 should be set
to 0.
Table 18. DIMM Bank Address Bit Definition
Bit(s)
0
2:1
15:7
31:23
Bank n
1 = Enable
0 = Disable
Address Mode (modes 00 and 11 are reserved)
Address Mask — Size of this bank
Base Address — Starting address of this bank
It is important that the registers place the largest logical bank
of memory in the lowest address space and then progress in
order to higher address space with the smaller sized banks.
152
DDR SDRAM Interface
Chapter 3