AMD-761 Datasheet, PDF (107/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Table 10. DDR Memory Base Address Register Locations
Memory Base Address Register 0
Memory Base Address Register 1
Memory Base Address Register 2
Memory Base Address Register 3
Memory Base Address Register 4
Memory Base Address Register 5
Memory Base Address Register 6
Memory Base Address Register 7
Dev0:F0:0xC0
Dev0:F0:0xC4
Dev0:F0:0xC8
Dev0:F0:0xCC
Dev0:F0:0xD0
Dev0:F0:0xD4
Dev0:F0:0xD8
Dev0:F0:0xDC
31
30
Bit
Reset
X
X
R/W
23
22
Bit CS_Base
Reset
X
0
R/W
R/W
15
14
Bit
Reset
X
X
R/W
7
6
Bit CS_Mask
Reset
X
0
R/W
R/W
29
28
27
CS_Base
X
X
X
R/W
21
20
19
Reserved
0
0
0
R
13
12
11
CS_Mask
X
X
X
R/W
5
4
3
Reserved
0
0
0
R
26
25
X
X
18
17
0
0
10
9
X
X
2
1
Addr_Mode
X
X
R/W
24
X
16
0
8
X
0
CS_En
X
Register Description
Note that these registers are not initialized at reset time, but must be initialized by BIOS for proper operation. This action
should be done prior to attempting DRAM access.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
95