AMD-761 Datasheet, PDF (190/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
SW_Recal
Use_Act_Dly
required (rather than a percentage of the clock period). To
determine the number of buffer delays, software must first
read the Clk_Dly bits and scale this value for the required
Act_Dly. For example, if Clk_Dly is 75 buffer delays at 100
MHz, and the BIOS desires a delay of 2.1 ns, the following is the
derivation of the Act_Dly value:
„ 75 buffer delays = half-period of system clock = 5 ns
„ 2.1 ns = 2.1 / 5 x 75 = 31.5 buffer delays
„ The Act_Dly value is either 31 or 32 (depending on rounding
desired) = 0x1F or 0x20.
The AMD-761 system controller provides a configuration bit
(Act_Dly_Inh) that inhibits the auto calibration state machine
from updating the Act_Dly values after the computation of
Clk_Dly and Cal_Dly is completed. If this mode is used, the
PDLs (Act_Dly values) are not updated with new Cal_Dly
values (whether auto-calibration is enabled or whether
software initiates a re-calibration). However, the PDLs are
always updated at reset. Upon exit from self-refresh, the
Act_Dly_Inh bit determines whether the PDLs are updated or
not. This feature can be useful for diagnostic purposes.
The Software Re-calibration bit (Dev 0:F1:0x40, bit [7])
provides a way for software to force a re-calibration cycle. This
action is allowed only when the auto calibration feature is
disabled. A re-calibration is forced when this bit is written to a
1b. This bit also provides status by being cleared when the
calibration has completed. BIOS may find it useful to be aware
of the completion of the calibration, although from a functional
perspective, the DDR memory controller does not require it.
When the re-calibration is complete, the hardware recomputes
the Cal_Dly values for all PDLs, based on the values of their
SW_Cal_Dly fields.
The Use Actual Delay bit (Dev 0:F1:0x40, bit [6]) provides a
way for software to change the PDL setting manually, which is
done by updating the Act_Dly field directly. BIOS should set
this bit to indicate to the hardware that it has written to the
Act_Dly fields and wants to update the PDLs (all 18) with the
newly written Act_Dly values. This method should be used only
when SW_Recal and Auto_Cal_En bits are not set. If
Auto_Cal_En is set, writes to this bit are ignored.
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DDR SDRAM Interface
Chapter 3