AMD-761 Datasheet, PDF (183/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Table 29. AMD-761™ System Controller ECC Behavior (with ECC Enabled)
Operation
ECC
Generated By:
AMD Athlon™ Processor System Bus Read
DRAM
AMD Athlon Processor System Bus Full Quadword Writes
AMD Athlon Processor System Bus Partial Quadword Writes
AMD Athlon
Processor
AMD-761 System
Controller
RMW on each QW
PCI/APCI/GART³ Read
DRAM
PCI/APCI/GART³ Full Quadword Writes
AMD-761 System
Controller
PCI/APCI/GART³ Partial Quadword Writes
AMD-761 System
Controller
RMW on each QW
Notes:
1. Single-bit error (SBE).
2. The data read from memory is checked and corrected before the merge/write.
3. APCI =Alternate PCI on AGP interface.
4. The scrubbing circuit detects, corrects read errors, and writes the corrected data to memory.
ECC
Checked By:
AMD-761™ Sys-
tem Controller
and AMD Athlon
Processor
SBEs¹
Corrected By:
AMD Athlon
Processor
None
None
AMD-761 System AMD-761 System
Controller²
Controller²
AMD-761
System
Controller
AMD-761 System
Controller
None
None
AMD-761
System
Controller²
AMD-761 System
Controller²
Memory scrubbing not only corrects single-bit errors to the
requesters and detects multiple-bit errors, but also writes the
corrected single-bit error value back into memory when this
feature is enabled. Refer to “ECC_Mode” on page 172 for more
information regarding the memory scrubbing feature and
configuration.
In addition to the status bits and chip-select identification, the
AMD-761 system controller allows single-bit and/or multiple-
bit errors to optionally assert SERR# to allow monitoring,
logging, and analysis of ECC errors by software. SysECCEn bit
should be set in the AMD Athlon processor when setting
"Report ECC Syndrome case." SysECCEn has an MSR address
of MSR C001_0010[15].
Chapter 3
DDR SDRAM Interface
171