AMD-761 Datasheet, PDF (28/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
2.3
2.3.1
16
Address Decoding
A consistent view of memory and PCI devices is enforced by
decoding logic in the AMD-761 system controller in the
AMD Athlon processor system bus and PCI interfaces.
Socket2000 Address Decoding
The AMD-761 system controller must consider both the
AMD Athlon processor system bus SysAddOut field and the
command field when deciding what to do with a given
command. This AMD Athlon processor system bus decoding is
summarized as follows:
„ SysAddOut MSB = 0 and command is a block command,
DRAM is accessed:
• If SysAddOut [31:0] falls between Dev0:BAR0 and
Dev0:BAR0+Len, address is to AGP virtual address space
and needs to passed through the GART before
presentation to DRAM.
„ SysAddOut MSB = 1 and command is a masked write
command (WrQWs, WrLWs, WrBytes), DRAM is accessed:
• If SysAddOut [31:0] falls between Dev0:BAR0 and
Dev0:BAR0+Len, address is to AGP virtual address space
and needs to passed through the GART before
presentation to DRAM.
„ SysAddOut MSB = 0 and SysAddOut [35:32] = 0 and
command is a masked command, PCI memory-mapped I/O is
accessed:
• Using Dev0:F0:0x14, BAR1, send to the AMD-761 system
controller memory-mapped GART control registers (see
Section 2.5 on page 138).
• Memory range address decoding, send to either PCI or
AGP/PCI using address bits [31:0] based on the
following:
• Dev1:0x20, 0x24 (see “AGP/PCI Memory Limit and
Base (Dev1:0x20)” on page 131 and “AGP/PCI
Prefetchable Memory Limit and Base (Dev1:0x24)”
on page 133).
• Dev 0:F0:0x84 AGP VGA BIOS bits, see “Bit
Definitions PCI Arbitration Control (Dev0:F0:0x84)”
on page 71).
AMD-761™ System Controller Programmer’s Interface
Chapter 2