AMD-761 Datasheet, PDF (124/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions
Bit Name
31–30 Reserved
29–27 PSlewCMDB
26–24 NSlewCMDB
23–20 Reserved
19–18 PDrvCMDB
17–16 NDrvCMDB
15–14 Reserved
DDR CMDB/CMDA Pad Configuration (Dev0:F1:0x94)
Function
Reserved
Command B Rising Edge Slew Rate
These bits control the rising edge slew rate of the RASB#, CASB#, WEB#, and CKEB# pins.
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
Command B Falling Edge Slew Rate
These bits control the falling edge slew rate of the RASB#, CASB#, WEB#, and
CKEB# pins.
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
Reserved
Command B P Transistor Drive Strength
These bits control the P transistor drive strength of the RASB#, CASB#, WEB#, and CKEB#
pins.
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
Command B N Transistor Drive Strength
These bits control the N transistor drive strength of the RASB#, CASB#, WEB#, and
CKEB# pins.
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
Reserved
112
AMD-761™ System Controller Programmer’s Interface
Chapter 2