AMD-761 Datasheet, PDF (106/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Memory Base
Address Registers
(Dev0:F0:0xC0 to
0xDF)
The AMD-761 system controller DDR memory controller can
access up to eight banks of DRAM (four DIMMs, one bank per
side). These banks are controlled by eight chip selects. These
registers define how an incoming address is parsed to select
only one out of the eight chip selects. BIOS software is
responsible for correctly loading these registers based on data
returned from the serial presence detect ROM mechanism
through the SMBus implemented in the Southbridge. BIOS
software must adhere to the following rules when configuring
these registers:
„ The largest banks are configured first as the lowest
addressed memory, increasing addresses with decreasing
size of banks available.
„ Logically, a given chip-select N, is asserted when:
(Addr[31:23] & ~CSMaskN) == (CSBaseN & ~CSMaskN)
„ The smallest bank supported is 32 Mbytes.
See Table 10 on page 95.
94
AMD-761™ System Controller Programmer’s Interface
Chapter 2