AMD-761 Datasheet, PDF (62/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions
Bit Name
31–24 Reserved
23–20 Pval
19–16 NVal
15–12 BYP_P
11–8 BYP_N
7–5 SlewCntl
4 BYP
3-0 Reserved
Programming Notes
AMD Athlon™ System Bus Dynamic Compensation (Dev0:F0:0x50)
Function
Reserved
P Transistor Strength Value
This field reflects the P transistor strength value that was automatically written to the
AMD Athlon™ processor system bus I/O pads by the auto-compensation circuit. In bypass
mode (bit 4=1) this field returns the values in the BYP_P field (bits [15:12]). The P values
are active Low.
N Transistor Strength Value
This field reflects the N transistor strength value that was automatically written to the
AMD Athlon processor system bus I/O pads by the auto-compensation circuit. In bypass
mode (bit 4=1) this field returns the values in the BYP_N field (bits [11:8]). The N values
are active High.
Bypass Values P Driver
Bypass strength values for the P driver. The P values are active Low. A value of 0 on bit 3
for instance signifies that (2^3 + 1) or 9 legs of the P driver are active.
Bypass Values N Driver
Bypass strength values for the N driver. The N values are active High. A value of 1 on bit 3,
for instance signifies that (2^3 + 1) or 9 legs of the N driver are active.
Slew Rate Control
Slew rate control for AMD Athlon processor system bus.
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3 (default)
100 = Slew rate 4
101= Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
Bypass
Setting the bypass bit allows an external drive strength setting to be provided in the BYP_P
and BYP_N fields. Clearing this bit causes the drive strength to be provided by the
compensation circuit.
Reserved
50
AMD-761™ System Controller Programmer’s Interface
Chapter 2