AMD-761 Datasheet, PDF (121/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31–30 Reserved
29–27 PSlewCLK
26–24 NSlewCLK
23–20 Reserved
19–18 PDrvCLK
17–16 NDrvCLK
15–14 Reserved
DDR CLK/CS Pad Configuration (Dev0:F1:0x90)
Function
Reserved
Clocks Rising Edge Slew Rate
These bits control the rising edge slew rate of the CLKOUT[5:0] and CLKOUT[5:0]# pins.
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
Clocks Falling Edge Slew Rate
These bits control the falling edge slew rate of the CLKOUT[5:0] and CLKOUT[5:0]# pins.
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
Reserved
Clocks P Transistor Drive Strength
These bits control the P transistor drive strength of the CLKOUT[5:0] and
CLKOUT[5:0]# pins.
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
Clocks N Transistor Drive Strength
These bits control the N transistor drive strength of the CLKOUT[5:0] and
CLKOUT[5:0]# pins.
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
Reserved
Chapter 2
AMD-761™ System Controller Programmer’s Interface
109