AMD-761 Datasheet, PDF (68/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
DRAM Mode/Status
31
30
Bit Clk_Dis5 Clk_Dis4
Reset
0
0
R/W
29
28
Clk_Dis3 Clk_Dis2
0
0
R/W
27
Clk_Dis1
0
Dev0:F0:0x58
26
Clk_Dis0
0
25
SDRAM_Init
0
R/W1S
24
Reserved
0
R
23
22
21
20
19
18
Bit
Mode_Reg
_ Status
STR_Control
Burst_Ref_En Ref_Dis
Reset
0
0
0
X
X
X
R/W R/W1S
R/W
17
16
Cyc_Per_Ref
X
X
15
14
13
12
11
10
9
8
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
7
6
5
4
3
2
1
0
Bit CS7_X4Mode CS6_X4Mode CS5_X4Mode CS4_X4Mode CS3_X4Mode CS2_X4Mode CS1_X4Mode CS0_X4Mode
Reset
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register Description
This register provides general mode control and status reporting of the DRAM system.
Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper
operation. This action should be done prior to attempting DRAM access.
56
AMD-761™ System Controller Programmer’s Interface
Chapter 2