AMD-761 Datasheet, PDF (172/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Write Recovery
Write to Read
160
current. Byte 28 of the SPD defines the t_RRD timing parameter.
Refer to Table 25 on page 160 for typical settings.
The Write Recovery bits (Dev 0:F0:0x54, bit [25:24]) specify the
minimum amount of time that must occur from the last WRITE
command to a PRECHARGE command to the same internal
bank of the DDR device. This device timing parameter is not
specified in the SPD, but the recommended setting is 10b and
specifies two system clock cycles between a write command
and a precharge command to the same internal bank. Refer to
Table 25 on page 160 for typical settings.
The Write To Read bit (Dev 0:F0:0x54, bit [26]) specifies the
minimum amount of time that must occur between the last
WRITE command to a following READ command to the same
internal bank of the DDR device. This device timing parameter
is not specified in the SPD, but the recommended setting is 1b
and specifies two system clock cycles. Refer to Table 25 on
page 160 for typical settings.
Table 25. DDR Device Timing Values
Symbol
Name
SPD
Byte
Typical Value
Description
Minimum RAS to
t_RCD CAS Delay
29
0x0x0x54[1:0]
Has 2-bit fraction—see SPD
50h
definitions. 50h = 20 ns.
2 cycles @100 MHz,
3 @ 133 MHz.
Minimum Active to
Integer value. 50-ns require-
t_RAS Precharge Time
0x0x0x54[6:4]
30
32h
ment. 5 cycles @ 100 MHz,
7 @ 133 MHz.
Minimum Row
t_RP Precharge Time
0x0x0x54[8:7]
Has 2-bit fraction—see SPD
27
50h
definitions. 50h = 20 ns.
2 cycles @100 MHz,
3 @ 133 MHz.
Typically defined as t_RAS + t_RP.
t_RC
Bank Cycle Time
0x0x0x54[11:9]
41
SPD entry available soon.
7 cycles @ 100 MHz,
10 @133 MHz.
Minimum Row Active
t_RRD to Row Active Delay 28
0x0x0x54[23]
Has 2-bit fraction—see SPD
3Ch
definitions. 3Ch = 15 ns.
2 cycles @100 MHz and
133 MHz.
t_WR
Minimum Write to
Precharge Time
N/A
N/A
t_WTR
Minimum Write to
Read Time
N/A
N/A
DDR SDRAM Interface
Chapter 3