AMD-761 Datasheet, PDF (147/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
AGP/PCI Interrupt and Bridge Control
31
30
29
28
27
Bit
Reserved
Reset
0
0
0
0
0
R/W
R
23
22
21
Bit
Bridge_Fast Secon_Bus
_B2B_En _Reset
Mas_Abort
_Mode
Reset
0
R/W
0
0
R
20
Reserved
0
19
VGA_En
0
15
14
13
12
11
Bit
Int_Pin
Reset
0
0
0
0
0
R/W
R/W (See Note)
7
6
5
4
3
Bit
Int_Line
Reset
0
0
0
0
0
R/W
R/W
26
0
18
ISA_En
0
R/W
10
0
2
0
Dev1:0x3C
25
24
0
0
17
16
SERR_En Par_Resp_En
0
0
R
9
8
0
0
1
0
0
0
Register Description
Bit Definitions
Bit Name
31–24 Reserved
23 Bridge_Fast_
B2B_En
22 Secon_Bus_Reset
21 Mas_Abort_Mode
AGP/PCI Interrupt and Bridge Control (Dev1:0x3C)
Function
Reserved
Fast Back-to-Back Capable
This bit is always 0, indicating that the AMD-761™ system controller as a master is not
capable of generating fast back-to-back transactions to different agents on the
secondary bus.
Secondary Bus Reset
This bit is always 0. Reset for the secondary interface is done with the PCIRST# output of
the AMD-766™ peripheral bus controller.
Master Abort Mode
This bit is always 0. The response to a master abort is determined by the
RD_Data_Err_Dis bit, Dev0:F0:0x84 bit 12.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
135