AMD-761 Datasheet, PDF (76/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
BIU0 SIP
31
Bit Clk_Fwd_Offset
Reset
0
R/W
R/W
30
29
Data_Init_Cnt
28
27
Addr_Init_Cnt
Pinstrapping
R
Dev0:F0:0x64
26
25
24
Sys_Data_Even_Clk_Dly
23
22
21
Bit
Sys_Data_Odd_Clk_Dly
Reset
R/W
20
19
Sys_Data_Even_Dly
Pinstrapping
R
18
17
Sys_Data_Odd_Dly
16
Sys_Addr_Dly
15
14
Bit Sys_Addr_Dly
Reset
R/W
13
12
11
SysDC_Dly
Pinstrapping
R
10
9
8
Sys_Addr_Clk_Dly
7
6
Bit
Sys_Rst_Clk_Offset
Reset
0
0
R/W
5
4
3
2
1
0
Sys_Data_Rec_Mux_PreLd
Sys_Addr_Rec_Mux_PreLd
Pinstrapping
R
Register Description
This register provides visibility to the serial initialization packet delivered to the AMD Athlon™ processor during the
AMD Athlon processor system bus connect protocol.
64
AMD-761™ System Controller Programmer’s Interface
Chapter 2