AMD-761 Datasheet, PDF (184/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
3.7.1
ECC and Memory Scrubbing Configuration
SERR_Enable
The System Error Enable bits (Dev 0:F0:0x48, bits [15:14])
control the AMD-761 system controller reporting of ECC errors
to the system via the SERR# pin on the PCI bus. Note that
SERR# assertion is still subject to the normal PCI SERR#
Enable (Dev 0:F0:0x04, bit [8]). Error reporting options are as
follow:
„ 00 = SERR# assertion disabled
„ X1 = Multiple bit errors force SERR# assertion
„ 1X = Single bit errors force SERR# assertion
ECC_Diag
The Error Correcting Code Diagnostic Mode Enable (Dev
0:F0:0x48, bit [12]) provides a way to purposely corrupt the
ECC check bits. When this mode is enabled, the AMD-761
system controller always writes 0x00h to the ECC check bit
byte. During partial writes, the RMW sequence still occurs, but
the ECC bits are always written to 0x00. This bit is useful for
logic testing and ECC driver development. A check bit value of
0x00 is a valid check bit code, so care should be used to not
corrupt a location where the user does not expect this valid
check bit value to exist. In the ECC_Diag mode, the AMD-761
system controller always writes 0x00 to the ECC byte to aid
testing of the ECC logic.
For reads, the ECC circuitry is unaffected by the ECC_Diag bit.
The ECC code returned from memory is checked, and errors
are reported in the ECC_Status bits as usual. Correction is not
performed in this mode to PCI, AGP, APC, or GART. However,
as mentioned earlier, because the AMD-761 system controller
simply passes ECC and read data information directly to the
AMD Athlon processor, the processor may correct this data if
this feature is enabled in the processor.
ECC_Mode
The Error Correcting Code mode bits enable a specific ECC
mode. These fields can be used in the following cases:
„ Disable ECC checking. In this mode, ECC is neither
generated nor maintained in the memory, and correction is
not performed. This mode is intended for memory systems
that are only 64 bits in width.
„ Enable ECC error checking mode only where data is still
checked and errors are still reported, but data destined for
the PCI or APCI/GART is not corrected. This approach
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DDR SDRAM Interface
Chapter 3