AMD-761 Datasheet, PDF (109/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
2.4.4
Table 12.
Device 0, Function 1: DDR PDL Configuration Registers
The registers defined in this section are required to implement
Double Data Rate (DDR) DRAM in the AMD-761 system
controller Northbridge. The function 1 registers control the 18
DDR programmable delay lines (PDL). In Table 12, the column
entitled Offset consists of the register number specified in the
Configuration Address register bits [7:2] concatenated with
0b00 to form a simple 1-byte offset.
Device 0, Function 1 Configuration Register Map
DDR PDL Registers (Device 0, Function 1)
Reserved
DDR PDL Calibration Control
DDR PDL Configuration 0
DDR PDL Configuration 1
DDR PDL Configuration 2
DDR PDL Configuration 3
DDR PDL Configuration 4
DDR PDL Configuration 5
DDR PDL Configuration 6
DDR PDL Configuration 7
DDR PDL Configuration 8
DDR PDL Configuration 9
DDR PDL Configuration 10
DDR PDL Configuration 11
DDR PDL Configuration 12
DDR PDL Configuration 13
DDR PDL Configuration 14
DDR PDL Configuration 15
DDR PDL Configuration 16
DDR PDL Configuration 17
DDR MDAT/DQS Pad Configuration
DDR CLK/CS Pad Configuration
DDR CMDB/CMDA Pad Configuration
DDR MAB/MAA Pad Configuration
Reserved
Offset
0x00 to 0x3F
0x40 to 0x43
0x44 to 0x47
0x48 to 0x4B
0x4C to 0x4F
0x50 to 0x53
0x54 to 0x57
0x58 to 0x5B
0x5C to 0x5F
0x60 to 0x63
0x64 to 0x67
0x68 to 0x6B
0x6C to 0x6F
0x70 to 0x73
0x74 to 0x77
0x78 to 0x7B
0x7C to 0x7F
0x80 to 0x83
0x84 to 0x87
0x88 to 0x8B
0x8C to 0x8F
0x90 to 0x93
0x94 to 0x97
0x98 to 0x9B
0x9C to 0xFF
Reference
“Dev0:F1:0x40” on
page 98
“Dev0:F1:0x44” on
page 101
“Dev0:F1:0x8C” on
page 104
“Dev0:F1:0x90” on
page 108
“Dev0:F1:0x94” on
page 111
“Dev0:F1:0x98” on
page 114
Chapter 2
AMD-761™ System Controller Programmer’s Interface
97