AMD-761 Datasheet, PDF (134/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions (Continued)
AGP/PCI Command and Status (Dev1:0x04)
Bit Name
Function
8 SERR
System Error Enable
When set, this bit enables the SERR# output. When clear, this bit disables the SERR#
output. The AGP A_SERR# is an input to the AMD-761™ system controller. The AMD-761
system controller receives AGP A_SERR#, ORs it with the normal PCI SERR#, and asserts it
to the AMD-766™ peripheral bus controller for possible error interrupt generation. Refer
to Table 7 on page 34 for details about SERR# assertion and status.
7 STEP
Address Stepping
This bit is always 0 because the AMD-761 system controller does not perform
address stepping.
6 PERR
Parity Error Response
This bit is always 0 because the AMD-761 system controller does not report data
parity errors.
5 VGA
VGA Palette Snoop Enable
This bit is always 0, indicating that the AMD-761 system controller does not snoop the VGA
palette address range.
4 MWINV
Memory Write and Invalidate Enable
This bit is always 0 because the AMD-761 system controller does not generate memory
write and invalidate commands.
3 SCYC
Special Cycle
This bit is always 0 because the AMD-761 system controller ignores PCI special cycles.
2 MSTR
Bus Master Enable
When this bit is set, the AMD-761 system controller accepts DMA accesses from the
AGP interface.
1 MEM
Memory Access Enable
When set, the AMD-761 system controller forwards AMD Athlon™ processor system bus
accesses that reference AGP memory space onto the AGP bus (see “Dev1:0x20” on
page 130).
0 I/O
I/O Access Enable
When set, the AMD-761 system controller forwards CPU accesses that reference AGP I/O
space onto the AGP bus (see “Dev1:0x1C” on page 127).
Programming Notes
122
AMD-761™ System Controller Programmer’s Interface
Chapter 2