AMD-761 Datasheet, PDF (200/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
controlled state that allows snooping of the processor cache.
If the AMD Athlon processor system bus is disconnected,
the processor enters a very low-power state.
The first option requires no special setup in the AMD-761
system controller other than to write a 0 to the
Stp_Grant_Discon_En bit in the BIU Status/Control register
(Dev 0:F0:0x60, bit 17). This action causes the AMD-761 system
controller to react to the Stop Grant special cycle on the
AMD Athlon processor system bus simply by forwarding the
cycle to the PCI bus, but not attempting any processor
disconnect. No significant power savings occur in this mode.
When this option is selected, the BIOS should not declare
support for the C2 state in the Fixed ACPI Description Table.
The second option requires that the following AMD-761 system
controller configuration bits be initialized:
„ The Stp_Grant_Discon_En must be set in the BIU
Status/Control register. When this bit is set, the AMD-761
system controller flushes internal queues after receiving
the Stop Grant special cycle, force the DDR DRAM into self-
refresh mode, and forward the Stop Grant special cycle to
the PCI bus to the Southbridge.
„ DRAM refresh must be enabled by writing a 0 to the
Ref_Dis test bit in the DRAM Mode/Status register (Dev
0:F0:0x58, bit 19).
„ Self-refresh must be enabled by writing a 1 to the Self_Ref_En
bit in the Status/Control register (Dev 0:F0:0x70, bit 18).
DMA cycles initiated from the PCI bus or AGP interface’s PCI
bus can be probed in the C2 state. When a cacheable access is
initiated on these interfaces, the AMD-761 system controller
initiates a connect sequence on the AMD Athlon system bus
via the PROCRDY/CONNECT protocol.
This mode requires specific configuration registers in the to be
initialized for proper generation of the STPCLK# signal and
resume events.
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Power Management
Chapter 4