AMD-761 Datasheet, PDF (70/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions (Continued)
DRAM Mode/Status (Dev0:F0:0x58)
Bit Name
Function
25 SDRAM_Init
SDRAM Initialization
This bit is used by the BIOS to tell the SDRAM controller to start the SDRAM initialization
sequence. Once set, this bit cannot be reset. The BIOS should first program the SDRAM
timing registers and set the output buffer drive strength. After that, it should set this bit.
24 Reserved
Reserved
23 Mode_Reg_Status Mode Register Status
0 = Off/done
1 = Set
When clear, the Mode register write is disabled and/or Mode register write done. When
set, the Mode register write is enabled. Configuration bits t_CL must be set before this bit is
asserted. BIOS software sets this bit for write to the SDRAM Mode register. The memory
controller clears this bit when it has issued the Mode register write to the SDRAM.
22–21 STR_Control
Suspend to RAM Control
These bits are used to allow the BIOS to communicate the power-up sequence to the
AMD-761™ system controller memory controller and power management logic, as
follows:
00 = Default. These bits are cleared to this state any time the RESET# pin is asserted.
The AMD-761 memory controller always drives the CKE pins inactive (Low) while
these bits are Low.
01 = BIOS sets this pattern after the system resumes from S4 (suspend to disk), S5 (soft
off), or mechanical off states. This action causes the AMD-761 memory controller
to assert the CKE pins and follow the normal sequence for DDR DRAM
initialization after power-on.
1X = BIOS sets this pattern when the system is resuming from the S3 (suspend to RAM)
state. This action causes the AMD-761 memory controller to exit self-refresh while
preserving all memory data.
20 Burst_Ref_En Burst Refresh Enable
0 = AMD-761 system controller does not burst refreshes.
1 = AMD-761 system controller queues up to four refreshes before issuing.
Refreshes are only queued during long sequences of operations to the same
memory device.
19 Ref_Dis
Refresh Disable
This bit is provided for system debug, and should be cleared for normal operation.
0 = Refresh enabled (normal operation)
1 = Refresh disabled (debug only)
18
Reserved
58
AMD-761™ System Controller Programmer’s Interface
Chapter 2