AMD-761 Datasheet, PDF (45/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31 PERR_Rcv
30 SERR_Sent
29 Mas_ ABRT
28 Trgt_ABRT
27 Trgt_ABRT_
Signaled
26—25 DEVSEL_Timing
24 Data_PERR
23 Fast B2B
22 UDF
21 66M
20 Cap_Lst
19–10 Reserved
9 FBACK
8 SERR
PCI Command and Status (Dev0:F0:0x04)
Function
Detected Parity Error
This bit is always 0 because the AMD-761™ system controller does not support data
parity checking.
Signaled System Error
This bit is set whenever the AMD-761 system controller generates a system error and
asserts the SERR# line (ECC, GART error). This bit is cleared by writing a 1. Refer to Table 7
on page 34 for details about SERR# assertion and status.
Received Master Abort
This bit is set whenever a CPU to PCI transaction (except for a special cycle) is terminated
due to a master abort. This bit is cleared by writing a 1.
Received Target Abort
This bit is set whenever a CPU to PCI transaction (except for a special cycle) is terminated
due to a target abort. This bit is cleared by writing a 1.
Signaled Target Abort
This bit is always 0 because the AMD-761 system controller does not terminate
transactions with target aborts.
DEVSEL# Timing
This bit field defines the timing of DEVSEL# on the AMD-761 system controller. The
AMD-761 system controller supports medium DEVSEL# timing.
Data Parity Error
This bit is always 0 because the AMD-761 system controller does not report parity errors.
Fast Back-to-Back Capable
This bit is always 0, indicating that the AMD-761 system controller as a target is not
capable of accepting fast back-to-back transactions when the transactions are not to the
same agent.
User-Definable Features
This bit is always 0, indicating that UDF is not supported on the AMD-761 system
controller.
66-MHz Capable
This bit is always 0, indicating that the AMD-761 system controller is not 66-MHz capable.
Capabilities List
This bit is set to indicate that this device’s configuration space supports a capabilities list.
Reserved
Fast Back-to-Back to Different Devices Enable
This bit is always 0, because the AMD-761 system controller does not allow generation of
fast back-to-back transactions to different agents.
System Error Enable
0 = SERR# driver disabled
1 = SERR# driver enabled
Refer to Table 7 for details about SERR# assertion and status.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
33