AMD-761 Datasheet, PDF (39/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
2.4.3
Table 6.
Device 0: PCI Configuration Registers
In Table 6, the column entitled Offset consists of the register
number specified in the Configuration Address register bits
[7:2] concatenated with 0b00 to form a simple 1-byte offset.
Reserved configuration registers return 0 when read.
Device 0, Function 0 Configuration Register Map
Host to PCI Bridge (Device 0, Function 0)
Device ID
Vendor ID
Status
Command
Class Code = 0x060000
Revision ID
Reserved
Header Type Latency Timer
Reserved
BAR0 - AGP Virtual Address Space
BAR1 - GART Memory-Mapped Control Registers Pointer
Reserved
Reserved
Reserved
Reserved
Capabilities
Pointer: A0
Extended BIU Control
ECC Mode/Status
PCI Control
AMD Athlon™ Processor System Bus Dynamic Compensation
DRAM Timing
DRAM Mode/Status
Reserved
BIU0 Status/Control
BIU0 SIP
Offset
0x00–0x03
0x04–0x07
0x08–0x0B
0x0C–0x0F
0x10–0x13
0x14–0x17
0x18–0x1B
0x1C–0x33
0x34–0x37
0x38–0x43
0x44–0x53
0x48–0x4B
0x4C–0x4F
0x50–0x53
0x54–0x57
0x58–0x5B
0x5C–0x5F
0x60–0x63
0x64–0x67
Reference
“Dev0:F0:0x00”
on page 30
“Dev0:F0:0x04”
on page 32
“Dev0:F0:0x08”
on page 35
“Dev0:F0:0x0C”
on page 36
“Dev0:F0:0x10”
on page 37
“Dev0:F0:0x14”
on page 39
“Dev0:F0:0x34”
on page 41
“Dev0:F0:0x44”
on page 42
“Dev0:F0:0x48”
on page 44
“Dev0:F0:0x4C”
on page 47
“Dev0:F0:0x50”
on page 49
“Dev0:F0:0x54”
on page 51
“Dev0:F0:0x58”
on page 56
“Dev0:F0:0x60”
on page 61
“Dev0:F0:0x64”
on page 64
Chapter 2
AMD-761™ System Controller Programmer’s Interface
27